1. Technical Field
The present disclosure relates to electronic design automation (EDA). More specifically, the present disclosure relates to methods and apparatuses for determining a robustness metric for a circuit design implementation.
2. Related Art
The slack at an endpoint of a circuit design implementation is equal to the difference between the arrival time and the required time at the endpoint. A slack is a violating slack if the slack value is less than a violation threshold. Of all the paths that end at the endpoint, the path with the worst slack is called the critical path for that endpoint.
Often times the RTL synthesis or place-and-route tool cannot meet the desired speed requirements as specified by the user, or the desired speed is not achievable. In these cases, the slack at the endpoint with the worst timing is a violating slack, and is known as the worst negative slack (WNS). The WNS is an important metric that is often used for comparing designs.
Note that violating slack values which are better than the WNS do not limit the speed at which the circuit can operate. However, these slack values can indicate the amount of work required for design closure (in terms of adjusting the floor-plan, re-writing the RTL, adjusting the constraints, and so on). Further, these critical violating paths whose slacks are better than the WNS may become the worst critical paths at a later stage in the design flow because of modeling variability that is inherent in the design flow. A robust circuit design is one that is optimized for all violating paths.
The WNS is not a good indicator of the robustness of the circuit design. Some conventional approaches use the total negative slack (TNS) as an indicator of design robustness. TNS is computed by summing up the violating slacks at the endpoints of the design. Unfortunately, conventional TNS-based metrics are poor indicators of robustness. Specifically, some conventional approaches do not provide any indication of the magnitude of the change in the TNS. Other approaches provide the percentage change in the TNS value relative to the original TNS value. However, these approaches can produce highly misleading results.
Hence, what is needed are methods and apparatuses for computing a robustness metric for a circuit design.